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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-09-13 11:05:50 +0900 |
|---|---|---|
| committer | Boris Brezillon <boris.brezillon@free-electrons.com> | 2017-09-18 14:55:52 +0200 |
| commit | 14157f861437ebe2d624b0a845b91bbdf8ca9a2d (patch) | |
| tree | ee3b430a97c0516cd92455525419a3edc3db25d5 /drivers/mtd/nand/atmel | |
| parent | 882fd1577cbe7812ae3a48988180c5f0fda475ca (diff) | |
| download | op-kernel-dev-14157f861437ebe2d624b0a845b91bbdf8ca9a2d.zip op-kernel-dev-14157f861437ebe2d624b0a845b91bbdf8ca9a2d.tar.gz | |
mtd: nand: introduce NAND_ROW_ADDR_3 flag
Several drivers check ->chipsize to see if the third row address cycle
is needed. Instead of embedding magic sizes such as 32MB, 128MB in
drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since
nand_scan_ident() knows well about the device, it can handle this
properly. The flag is set if the row address bit width is greater
than 16.
Delete comments such as "One more address cycle for ..." because
intention is now clear enough from the code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers/mtd/nand/atmel')
| -rw-r--r-- | drivers/mtd/nand/atmel/nand-controller.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c index f25eca7..7bc8d20 100644 --- a/drivers/mtd/nand/atmel/nand-controller.c +++ b/drivers/mtd/nand/atmel/nand-controller.c @@ -718,8 +718,7 @@ static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column) nc->op.addrs[nc->op.naddrs++] = page; nc->op.addrs[nc->op.naddrs++] = page >> 8; - if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) || - (mtd->writesize <= 512 && chip->chipsize > SZ_32M)) + if (chip->options & NAND_ROW_ADDR_3) nc->op.addrs[nc->op.naddrs++] = page >> 16; } } |
