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authorJaehoon Chung <jh80.chung@samsung.com>2015-10-21 19:49:42 +0900
committerUlf Hansson <ulf.hansson@linaro.org>2015-10-29 11:00:43 +0100
commit7cc8d580228cc712edcf7a1856a3bdb38c164e83 (patch)
tree11fac7a50fe4073274dffebdd84f7e92ef4b9632 /drivers/mmc
parent98daafd8a09d9a514bc2166709731d659037003b (diff)
downloadop-kernel-dev-7cc8d580228cc712edcf7a1856a3bdb38c164e83.zip
op-kernel-dev-7cc8d580228cc712edcf7a1856a3bdb38c164e83.tar.gz
mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode
When card is running with DDR mode, dwmmc needs to set DDR_REG bit at UHS_REG register. Before this patch, dwmmc controller doesn't consider this. If this patch is not applied, CRC or other error shoulds be occurred. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/dw_mmc.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 57a9577..7a6cedb 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1293,6 +1293,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
/* DDR mode set */
if (ios->timing == MMC_TIMING_MMC_DDR52 ||
+ ios->timing == MMC_TIMING_UHS_DDR50 ||
ios->timing == MMC_TIMING_MMC_HS400)
regs |= ((0x1 << slot->id) << 16);
else
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