diff options
| author | Dong Aisheng <b29396@freescale.com> | 2013-11-04 16:38:26 +0800 |
|---|---|---|
| committer | Chris Ball <chris@printf.net> | 2014-01-13 12:48:07 -0500 |
| commit | d131a71c951088704eabe1529de99188c9e2c22c (patch) | |
| tree | 576e59f8888fddde5b5c331d25951e05fca89f6f /drivers/mmc | |
| parent | d433dc63182825538b85de6a85e2ea3fad7f2917 (diff) | |
| download | op-kernel-dev-d131a71c951088704eabe1529de99188c9e2c22c.zip op-kernel-dev-d131a71c951088704eabe1529de99188c9e2c22c.tar.gz | |
mmc: sdhci-esdhc-imx: tuning bits should not be cleared during reset
We should not clear tuning bits during reset or the SD3.0/eMMC4.5 card
working on UHS mode may not work after reset since the former tuning
settings was lost.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-esdhc-imx.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index d4ba277..d85a6a6 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -45,6 +45,8 @@ #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) /* Bits 3 and 6 are not SDHCI standard definitions */ #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 +/* Tuning bits */ +#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 /* dll control register */ #define ESDHC_DLL_CTRL 0x60 @@ -562,7 +564,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) * Do it manually here. */ if (esdhc_is_usdhc(imx_data)) { - writel(0, host->ioaddr + ESDHC_MIX_CTRL); + /* the tuning bits should be kept during reset */ + new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); + writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, + host->ioaddr + ESDHC_MIX_CTRL); imx_data->is_ddr = 0; } } |
