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author | Sahitya Tummala <stummala@codeaurora.org> | 2011-05-02 18:09:18 +0530 |
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committer | Chris Ball <cjb@laptop.org> | 2011-10-26 15:43:37 -0400 |
commit | 4a268e0879c4044523757b6ac94b56fc7955a116 (patch) | |
tree | 3397cdc9c1d95b215e6094e1629fc3a4e4c1ae30 /drivers/mmc/host/msm_sdcc.h | |
parent | 4a92fe80becbbee650cfad8457ad0e5cd97ed974 (diff) | |
download | op-kernel-dev-4a268e0879c4044523757b6ac94b56fc7955a116.zip op-kernel-dev-4a268e0879c4044523757b6ac94b56fc7955a116.tar.gz |
mmc: msm_sdcc: Use MCI_INT_MASK0 for PIO interrupts
Not all targets have IRQ1 line routed from the SD controller to
the processor. So we cannot rely on IRQ1 for PIO interrupts.
This patch moves all PIO interrupts to IRQ0 and enables the PIO
mode.
Signed-off-by: Murali Palnati <palnatim@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/host/msm_sdcc.h')
-rw-r--r-- | drivers/mmc/host/msm_sdcc.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h index fa626ed..402028d 100644 --- a/drivers/mmc/host/msm_sdcc.h +++ b/drivers/mmc/host/msm_sdcc.h @@ -140,6 +140,11 @@ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK|MCI_PROGDONEMASK) +#define MCI_IRQ_PIO \ + (MCI_RXDATAAVLBLMASK | MCI_TXDATAAVLBLMASK | MCI_RXFIFOEMPTYMASK | \ + MCI_TXFIFOEMPTYMASK | MCI_RXFIFOFULLMASK | MCI_TXFIFOFULLMASK | \ + MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK | \ + MCI_RXACTIVEMASK | MCI_TXACTIVEMASK) /* * The size of the FIFO in bytes. */ |