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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2014-06-02 10:10:04 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2014-07-09 11:25:57 +0200
commit9c34b73deec147a042c4bd871a373f76af70e38c (patch)
tree2649ee4b956c0d8fedfce41e9a59406909566b07 /drivers/mmc/host/mmci.c
parent3f4e6f7b9175e2914b82134c4a6a02825f4766db (diff)
downloadop-kernel-dev-9c34b73deec147a042c4bd871a373f76af70e38c.zip
op-kernel-dev-9c34b73deec147a042c4bd871a373f76af70e38c.tar.gz
mmc: mmci: Add Qcom specific rx_fifocnt logic.
MCIFIFOCNT register behaviour on Qcom chips is very different than the other pl180 integrations. MCIFIFOCNT register contains the number of words that are still waiting to be transferred through the FIFO. It keeps decrementing once the host CPU reads the MCIFIFO. With the existing logic and the MCIFIFOCNT behaviour, mmci_pio_read will loop forever, as the FIFOCNT register will always return transfer size before reading the FIFO. Also the data sheet states that "This register is only useful for debug purposes and should not be used for normal operation since it does not reflect data which may or may not be in the pipeline". This patch implements a qcom specific get_rx_fifocnt function which is implemented based on status register flags. Based on qcom_fifo flag in variant data structure, the corresponding get_rx_fifocnt function is selected. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/mmci.c')
-rw-r--r--drivers/mmc/host/mmci.c30
1 files changed, 28 insertions, 2 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 2e6075f..063136d 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -73,6 +73,7 @@ static unsigned int fmax = 515633;
* @busy_detect: true if busy detection on dat0 is supported
* @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
* @explicit_mclk_control: enable explicit mclk control in driver.
+ * @qcom_fifo: enables qcom specific fifo pio read logic.
*/
struct variant_data {
unsigned int clkreg;
@@ -95,6 +96,7 @@ struct variant_data {
bool busy_detect;
bool pwrreg_nopower;
bool explicit_mclk_control;
+ bool qcom_fifo;
};
static struct variant_data variant_arm = {
@@ -992,15 +994,34 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
}
}
+static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
+{
+ return remain - (readl(host->base + MMCIFIFOCNT) << 2);
+}
+
+static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
+{
+ /*
+ * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
+ * from the fifo range should be used
+ */
+ if (status & MCI_RXFIFOHALFFULL)
+ return host->variant->fifohalfsize;
+ else if (status & MCI_RXDATAAVLBL)
+ return 4;
+
+ return 0;
+}
+
static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
{
void __iomem *base = host->base;
char *ptr = buffer;
- u32 status;
+ u32 status = readl(host->base + MMCISTATUS);
int host_remain = host->size;
do {
- int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
+ int count = host->get_rx_fifocnt(host, status, host_remain);
if (count > remain)
count = remain;
@@ -1489,6 +1510,11 @@ static int mmci_probe(struct amba_device *dev,
if (ret)
goto host_free;
+ if (variant->qcom_fifo)
+ host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
+ else
+ host->get_rx_fifocnt = mmci_get_rx_fifocnt;
+
host->plat = plat;
host->variant = variant;
host->mclk = clk_get_rate(host->clk);
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