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| author | Arindam Nath <arindam.nath@amd.com> | 2011-05-05 12:19:00 +0530 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2011-05-24 23:53:44 -0400 |
| commit | 758535c4e3cdd2b5b09565d9651aaa541aac3de8 (patch) | |
| tree | 68675c722181a7d83e19830ee5b1bd50399b8d64 /drivers/mmc/core/sd.c | |
| parent | d6d50a15a2897d4133d536dd4343b5cf21163db3 (diff) | |
| download | op-kernel-dev-758535c4e3cdd2b5b09565d9651aaa541aac3de8.zip op-kernel-dev-758535c4e3cdd2b5b09565d9651aaa541aac3de8.tar.gz | |
mmc: sdhci: reset sdclk before setting high speed enable
As per Host Controller spec v3.00, we reset SDCLK before setting
High Speed Enable, and then set it back to avoid generating clock
gliches. Before enabling SDCLK again, we make sure the clock is
stable, so we use sdhci_set_clock().
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/core/sd.c')
0 files changed, 0 insertions, 0 deletions
