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author | Nishanth Menon <nm@ti.com> | 2012-02-22 20:03:45 -0600 |
---|---|---|
committer | Samuel Ortiz <sameo@linux.intel.com> | 2012-03-06 18:46:48 +0100 |
commit | 3f8349e6e98ba0455437724589072523865eae5e (patch) | |
tree | 2d7c157d86aa6345e1c3cf8719e41b3897531fb3 /drivers/mfd | |
parent | 91d6a9a6c0d98ef6daeaf229e5acada652b4f6f0 (diff) | |
download | op-kernel-dev-3f8349e6e98ba0455437724589072523865eae5e.zip op-kernel-dev-3f8349e6e98ba0455437724589072523865eae5e.tar.gz |
mfd: Clear twl6030 IRQ status register only once
TWL6030 family of PMIC use a shadow interrupt status register
while kernel processes the current interrupt event.
However, any write(0 or 1) to register INT_STS_A, INT_STS_B or
INT_STS_C clears all 3 interrupt status registers.
Since clear of the interrupt is done on 32k clk, depending on I2C
bus speed, we could in-adverently clear the status of a interrupt
status pending on shadow register in the current implementation.
This is due to the fact that multi-byte i2c write operation into
three seperate status register could result in multiple load
and clear of status and result in lost interrupts.
Instead, doing a single byte write to INT_STS_A register with 0x0
will clear all three interrupt status registers without the related
risk.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd')
-rw-r--r-- | drivers/mfd/twl6030-irq.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c index c6b456a..aa367a2 100644 --- a/drivers/mfd/twl6030-irq.c +++ b/drivers/mfd/twl6030-irq.c @@ -185,8 +185,17 @@ static int twl6030_irq_thread(void *data) } local_irq_enable(); } - ret = twl_i2c_write(TWL_MODULE_PIH, sts.bytes, - REG_INT_STS_A, 3); /* clear INT_STS_A */ + + /* + * NOTE: + * Simulation confirms that documentation is wrong w.r.t the + * interrupt status clear operation. A single *byte* write to + * any one of STS_A to STS_C register results in all three + * STS registers being reset. Since it does not matter which + * value is written, all three registers are cleared on a + * single byte write, so we just use 0x0 to clear. + */ + ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A); if (ret) pr_warning("twl6030: I2C error in clearing PIH ISR\n"); |