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| author | Ulf Hansson <ulf.hansson@linaro.org> | 2013-05-14 15:14:55 +0200 |
|---|---|---|
| committer | Samuel Ortiz <sameo@linux.intel.com> | 2013-05-17 00:42:34 +0200 |
| commit | e9d7b4b5691cac4dce6c5eed9e217e50e24edef7 (patch) | |
| tree | 02a1dbba87708c64445379937b7497487dfb8fe0 /drivers/mfd | |
| parent | 0b8ebdb18888c55588b932f4f564b9c9529de627 (diff) | |
| download | op-kernel-dev-e9d7b4b5691cac4dce6c5eed9e217e50e24edef7.zip op-kernel-dev-e9d7b4b5691cac4dce6c5eed9e217e50e24edef7.tar.gz | |
mfd: db8500-prcmu: Update stored DSI PLL divider value
Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework was enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.
This patch makes sure the actual hw settings and the sw assumed
settings are matched.
Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson@stericsson.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd')
| -rw-r--r-- | drivers/mfd/db8500-prcmu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 5389368..66f8097 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -1613,6 +1613,8 @@ static unsigned long dsiclk_rate(u8 n) if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) divsel = dsiclk[n].divsel; + else + dsiclk[n].divsel = divsel; switch (divsel) { case PRCM_DSI_PLLOUT_SEL_PHI_4: |
