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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2014-05-06 11:46:10 +0300
committerLee Jones <lee.jones@linaro.org>2014-06-03 08:11:28 +0100
commitac8320c471e187d7fdc90f807199ff77c116a668 (patch)
tree19052d42fd12b3290a26a2d1c5f99aeba06a5d70 /drivers/mfd/mc13xxx-core.c
parenta58cc84cafa2376a2d5fcdb3d513327a2fb813c2 (diff)
downloadop-kernel-dev-ac8320c471e187d7fdc90f807199ff77c116a668.zip
op-kernel-dev-ac8320c471e187d7fdc90f807199ff77c116a668.tar.gz
mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk
When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be put in bypass mode. This will fix HPPLL use on boards with 19.2MHz mclk. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd/mc13xxx-core.c')
0 files changed, 0 insertions, 0 deletions
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