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authorAaron Sierra <asierra@xes-inc.com>2014-08-26 18:18:33 -0500
committerBrian Norris <computersforpeace@gmail.com>2014-11-05 14:45:53 -0800
commit096916610f415e07cfe71d71a391011c617be5ed (patch)
tree0e2c9596200462aff4a267607a134ba16f308d95 /drivers/memory
parentabb1cd00e6b7434e866f1f817b4994e1c7f1f16d (diff)
downloadop-kernel-dev-096916610f415e07cfe71d71a391011c617be5ed.zip
op-kernel-dev-096916610f415e07cfe71d71a391011c617be5ed.tar.gz
fsl_ifc: Support all 8 IFC chip selects
Freescale's QorIQ T Series processors support 8 IFC chip selects within a memory map backward compatible with previous P Series processors which supported only 4 chip selects. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/fsl_ifc.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c
index 3d5d792..410c397 100644
--- a/drivers/memory/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -61,7 +61,7 @@ int fsl_ifc_find(phys_addr_t addr_base)
if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
return -ENODEV;
- for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {
+ for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
if (cspr & CSPR_V && (cspr & CSPR_BA) ==
convert_ifc_address(addr_base))
@@ -213,7 +213,7 @@ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
static int fsl_ifc_ctrl_probe(struct platform_device *dev)
{
int ret = 0;
-
+ int version, banks;
dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
@@ -231,6 +231,15 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
goto err;
}
+ version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
+ FSL_IFC_VERSION_MASK;
+ banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
+ dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
+ version >> 24, (version >> 16) & 0xf, banks);
+
+ fsl_ifc_ctrl_dev->version = version;
+ fsl_ifc_ctrl_dev->banks = banks;
+
/* get the Controller level irq */
fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
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