diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2016-08-31 10:25:16 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2016-09-22 10:13:53 -0300 |
| commit | 438236e7c151ec797d433fd4c3e770f55cdc5d04 (patch) | |
| tree | 331a786c6b9331524231d3d4d1d25ce52cbd6572 /drivers/media | |
| parent | 6e7122a3c83ad468037e7f22f324feccb6252bf4 (diff) | |
| download | op-kernel-dev-438236e7c151ec797d433fd4c3e770f55cdc5d04.zip op-kernel-dev-438236e7c151ec797d433fd4c3e770f55cdc5d04.tar.gz | |
[media] exynos4-is: Add support for all required clocks
This patch adds 3 more clocks to Exynos4 ISP driver. Enabling them is
needed to make the hardware operational. Till now it worked only because
those clocks were registered with IGNORE_UNUSED flag and were enabled
by default after SoC reset.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'drivers/media')
| -rw-r--r-- | drivers/media/platform/exynos4-is/fimc-is.c | 3 | ||||
| -rw-r--r-- | drivers/media/platform/exynos4-is/fimc-is.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c index 13c779d..313ab10 100644 --- a/drivers/media/platform/exynos4-is/fimc-is.c +++ b/drivers/media/platform/exynos4-is/fimc-is.c @@ -52,6 +52,9 @@ static char *fimc_is_clocks[ISS_CLKS_MAX] = { [ISS_CLK_DRC] = "drc", [ISS_CLK_FD] = "fd", [ISS_CLK_MCUISP] = "mcuisp", + [ISS_CLK_GICISP] = "gicisp", + [ISS_CLK_PWM_ISP] = "pwm_isp", + [ISS_CLK_MCUCTL_ISP] = "mcuctl_isp", [ISS_CLK_UART] = "uart", [ISS_CLK_ISP_DIV0] = "ispdiv0", [ISS_CLK_ISP_DIV1] = "ispdiv1", diff --git a/drivers/media/platform/exynos4-is/fimc-is.h b/drivers/media/platform/exynos4-is/fimc-is.h index 3a82c6a..ee05da0 100644 --- a/drivers/media/platform/exynos4-is/fimc-is.h +++ b/drivers/media/platform/exynos4-is/fimc-is.h @@ -77,6 +77,9 @@ enum { ISS_CLK_DRC, ISS_CLK_FD, ISS_CLK_MCUISP, + ISS_CLK_GICISP, + ISS_CLK_PWM_ISP, + ISS_CLK_MCUCTL_ISP, ISS_CLK_UART, ISS_GATE_CLKS_MAX, ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX, |
