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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-22 19:24:17 -0700 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-22 19:24:17 -0700 |
commit | 0fd56c70334d7899edaee742ae49d9b893951376 (patch) | |
tree | 76b82ef119aa4a5ef8bbacb8256aeaba4277f7e1 /drivers/kvm/lapic.c | |
parent | 56d61a0e26c5a61c66d1ac259a59960295939da9 (diff) | |
parent | 49d3bd7e2b990e717aa66e229410b8f5096c4956 (diff) | |
download | op-kernel-dev-0fd56c70334d7899edaee742ae49d9b893951376.zip op-kernel-dev-0fd56c70334d7899edaee742ae49d9b893951376.tar.gz |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm:
KVM: Use new smp_call_function_mask() in kvm_flush_remote_tlbs()
sched: don't clear PF_VCPU in scheduler
KVM: Improve local apic timer wraparound handling
KVM: Fix local apic timer divide by zero
KVM: Move kvm_guest_exit() after local_irq_enable()
KVM: x86 emulator: fix access registers for instructions with ModR/M byte and Mod = 3
KVM: VMX: Force vm86 mode if setting flags during real mode
KVM: x86 emulator: implement 'movnti mem, reg'
KVM: VMX: Reset mmu context when entering real mode
KVM: VMX: Handle NMIs before enabling interrupts and preemption
KVM: MMU: Set shadow pte atomically in mmu_pte_write_zap_pte()
KVM: x86 emulator: fix repne/repnz decoding
KVM: x86 emulator: fix merge screwup due to emulator split
Diffstat (limited to 'drivers/kvm/lapic.c')
-rw-r--r-- | drivers/kvm/lapic.c | 38 |
1 files changed, 27 insertions, 11 deletions
diff --git a/drivers/kvm/lapic.c b/drivers/kvm/lapic.c index a190587..238fcad 100644 --- a/drivers/kvm/lapic.c +++ b/drivers/kvm/lapic.c @@ -494,12 +494,19 @@ static void apic_send_ipi(struct kvm_lapic *apic) static u32 apic_get_tmcct(struct kvm_lapic *apic) { - u32 counter_passed; - ktime_t passed, now = apic->timer.dev.base->get_time(); - u32 tmcct = apic_get_reg(apic, APIC_TMICT); + u64 counter_passed; + ktime_t passed, now; + u32 tmcct; ASSERT(apic != NULL); + now = apic->timer.dev.base->get_time(); + tmcct = apic_get_reg(apic, APIC_TMICT); + + /* if initial count is 0, current count should also be 0 */ + if (tmcct == 0) + return 0; + if (unlikely(ktime_to_ns(now) <= ktime_to_ns(apic->timer.last_update))) { /* Wrap around */ @@ -514,15 +521,24 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic) counter_passed = div64_64(ktime_to_ns(passed), (APIC_BUS_CYCLE_NS * apic->timer.divide_count)); - tmcct -= counter_passed; - if (tmcct <= 0) { - if (unlikely(!apic_lvtt_period(apic))) + if (counter_passed > tmcct) { + if (unlikely(!apic_lvtt_period(apic))) { + /* one-shot timers stick at 0 until reset */ tmcct = 0; - else - do { - tmcct += apic_get_reg(apic, APIC_TMICT); - } while (tmcct <= 0); + } else { + /* + * periodic timers reset to APIC_TMICT when they + * hit 0. The while loop simulates this happening N + * times. (counter_passed %= tmcct) would also work, + * but might be slower or not work on 32-bit?? + */ + while (counter_passed > tmcct) + counter_passed -= tmcct; + tmcct -= counter_passed; + } + } else { + tmcct -= counter_passed; } return tmcct; @@ -853,7 +869,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu) apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); } - apic->timer.divide_count = 0; + update_divide_count(apic); atomic_set(&apic->timer.pending, 0); if (vcpu->vcpu_id == 0) vcpu->apic_base |= MSR_IA32_APICBASE_BSP; |