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authorFelipe Balbi <balbi@ti.com>2014-09-15 16:15:06 -0500
committerTony Lindgren <tony@atomide.com>2014-09-16 14:45:00 -0700
commit9836ee9f87dc669c8ce2b24ba986600a6977ca8b (patch)
tree37ce853d4508b26a06be474a2d31aab9ffa66849 /drivers/irqchip
parent8bb3b375c8837ea73740883a90b1d7719b2653cc (diff)
downloadop-kernel-dev-9836ee9f87dc669c8ce2b24ba986600a6977ca8b.zip
op-kernel-dev-9836ee9f87dc669c8ce2b24ba986600a6977ca8b.tar.gz
irqchip: omap-intc: enable IP protection
When PROTECTION bit in enabled in PROTECTION register, INTC's registers are only accessible from privileged mode. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/irq-omap-intc.c22
1 files changed, 20 insertions, 2 deletions
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c
index e97b535..7681b13 100644
--- a/drivers/irqchip/irq-omap-intc.c
+++ b/drivers/irqchip/irq-omap-intc.c
@@ -51,6 +51,8 @@
#define INTCPS_NR_ILR_REGS 128
#define INTCPS_NR_MIR_REGS 3
+#define INTC_PROTECTION_ENABLE (1 << 0)
+
/*
* OMAP2 has a number of different interrupt controllers, each interrupt
* controller is identified as its own "bank". Register definitions are
@@ -290,12 +292,28 @@ static int __init omap_init_irq_legacy(u32 base)
return 0;
}
+static void __init omap_irq_enable_protection(void)
+{
+ u32 reg;
+
+ reg = intc_readl(INTC_PROTECTION);
+ reg |= INTC_PROTECTION_ENABLE;
+ intc_writel(INTC_PROTECTION, reg);
+}
+
static int __init omap_init_irq(u32 base, struct device_node *node)
{
+ int ret;
+
if (node)
- return omap_init_irq_of(node);
+ ret = omap_init_irq_of(node);
else
- return omap_init_irq_legacy(base);
+ ret = omap_init_irq_legacy(base);
+
+ if (ret == 0)
+ omap_irq_enable_protection();
+
+ return ret;
}
static asmlinkage void __exception_irq_entry
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