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| author | Will Deacon <will.deacon@arm.com> | 2014-06-24 18:26:26 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-07-02 11:55:49 +0100 |
| commit | a65217a4bcdb654e04fcc42b302d8a15708e14ce (patch) | |
| tree | 1affd8e038912b297f888f0ed84631a758968816 /drivers/iommu | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) | |
| download | op-kernel-dev-a65217a4bcdb654e04fcc42b302d8a15708e14ce.zip op-kernel-dev-a65217a4bcdb654e04fcc42b302d8a15708e14ce.tar.gz | |
iommu/arm-smmu: fix calculation of TCR.T0SZ
T0SZ controls the input address range for TTBR0, so use the input
address range rather than the output address range for the calculation.
For stage-2, this means using the output size of stage-1.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/arm-smmu.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 1599354..81e8ec2 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -800,6 +800,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg = TTBCR_TG0_64K; if (!stage1) { + reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; + switch (smmu->s2_output_size) { case 32: reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); @@ -821,7 +823,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) break; } } else { - reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; + reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; } } else { reg = 0; |
