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authorJoerg Roedel <joerg.roedel@amd.com>2011-12-07 14:34:02 +0100
committerJoerg Roedel <joerg.roedel@amd.com>2011-12-15 11:05:35 +0100
commit46277b75da1b6c57159496d536acc2e9352a7ee0 (patch)
tree6cabd9b79c7187fa755d694f96f1d712d2ad8807 /drivers/iommu
parent5c11ad95b5ba7d5a3675f3d5829a8131a13b33d5 (diff)
downloadop-kernel-dev-46277b75da1b6c57159496d536acc2e9352a7ee0.zip
op-kernel-dev-46277b75da1b6c57159496d536acc2e9352a7ee0.tar.gz
iommu/amd: Adapt IOMMU driver to PCI register name changes
The symbolic register names for PCI and PASID changed in PCI code. This patch adapts the AMD IOMMU driver to these changes. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/amd_iommu.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index a7cbcd4..d5074f4 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -176,8 +176,8 @@ static bool pci_iommuv2_capable(struct pci_dev *pdev)
{
static const int caps[] = {
PCI_EXT_CAP_ID_ATS,
- PCI_PRI_CAP,
- PCI_PASID_CAP,
+ PCI_EXT_CAP_ID_PRI,
+ PCI_EXT_CAP_ID_PASID,
};
int i, pos;
@@ -1978,13 +1978,13 @@ static int pri_reset_while_enabled(struct pci_dev *pdev)
u16 control;
int pos;
- pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
if (!pos)
return -EINVAL;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
- control |= PCI_PRI_RESET;
- pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
+ control |= PCI_PRI_CTRL_RESET;
+ pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
return 0;
}
@@ -2042,11 +2042,11 @@ bool pci_pri_tlp_required(struct pci_dev *pdev)
u16 control;
int pos;
- pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
if (!pos)
return false;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
return (control & PCI_PRI_TLP_OFF) ? true : false;
}
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