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authorWill Deacon <will.deacon@arm.com>2014-06-25 12:12:41 +0100
committerWill Deacon <will.deacon@arm.com>2014-07-03 15:50:22 +0100
commit9c5c92e35cf5c4f7ee523d62a6bf9d5dc290350b (patch)
tree977fab969cfe52fb9153c05de21bc6d46d4b8a19 /drivers/iommu/arm-smmu.c
parent44680eedf9409daf0fed618ae101f35d1f83d1a4 (diff)
downloadop-kernel-dev-9c5c92e35cf5c4f7ee523d62a6bf9d5dc290350b.zip
op-kernel-dev-9c5c92e35cf5c4f7ee523d62a6bf9d5dc290350b.tar.gz
iommu/arm-smmu: prefer stage-1 mappings where we have a choice
For an SMMU that supports both Stage-1 and Stage-2 mappings (but not nested translation), then we should prefer stage-1 mappings as we otherwise rely on the memory attributes of the incoming transactions for IOMMU_CACHE mappings. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu/arm-smmu.c')
-rw-r--r--drivers/iommu/arm-smmu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 2961b8c..7638b57 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -876,12 +876,12 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
*/
cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
start = smmu->num_s2_context_banks;
- } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
- cfg->cbar = CBAR_TYPE_S2_TRANS;
- start = 0;
- } else {
+ } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
start = smmu->num_s2_context_banks;
+ } else {
+ cfg->cbar = CBAR_TYPE_S2_TRANS;
+ start = 0;
}
ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
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