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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2014-03-05 18:54:18 -0600 |
|---|---|---|
| committer | Joerg Roedel <joro@8bytes.org> | 2014-03-24 16:45:59 +0100 |
| commit | a919a018cccf999aa56d7f9adeae0525b01b7434 (patch) | |
| tree | 2dc30421a1fff7a9bb26d0209aff36ba39a4998d /drivers/iommu/amd_iommu_types.h | |
| parent | e8d2d82d4a73f37b3270e4fd19ba83e48b589656 (diff) | |
| download | op-kernel-dev-a919a018cccf999aa56d7f9adeae0525b01b7434.zip op-kernel-dev-a919a018cccf999aa56d7f9adeae0525b01b7434.tar.gz | |
iommu/amd: Fix logic to determine and checking max PASID
In reality, the spec can only support 16-bit PASID since
INVALIDATE_IOTLB_PAGES and COMPLETE_PPR_REQUEST commands only allow 16-bit
PASID. So, we updated the PASID_MASK accordingly and invoke BUG_ON
if the hardware is reporting PASmax more than 16-bit.
Besides, max PASID is defined as ((2^(PASmax+1)) - 1). The current does not
determine this correctly.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Tested-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
Diffstat (limited to 'drivers/iommu/amd_iommu_types.h')
| -rw-r--r-- | drivers/iommu/amd_iommu_types.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index e400fbe..55ba46b 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -98,7 +98,12 @@ #define FEATURE_GLXVAL_SHIFT 14 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) -#define PASID_MASK 0x000fffff +/* Note: + * The current driver only support 16-bit PASID. + * Currently, hardware only implement upto 16-bit PASID + * even though the spec says it could have upto 20 bits. + */ +#define PASID_MASK 0x0000ffff /* MMIO status bits */ #define MMIO_STATUS_EVT_INT_MASK (1 << 1) @@ -696,8 +701,8 @@ extern unsigned long *amd_iommu_pd_alloc_bitmap; */ extern u32 amd_iommu_unmap_flush; -/* Smallest number of PASIDs supported by any IOMMU in the system */ -extern u32 amd_iommu_max_pasids; +/* Smallest max PASID supported by any IOMMU in the system */ +extern u32 amd_iommu_max_pasid; extern bool amd_iommu_v2_present; |
