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authorJack Morgenstein <jackm@mellanox.co.il>2005-12-15 19:59:01 -0800
committerRoland Dreier <rolandd@cisco.com>2005-12-15 19:59:01 -0800
commitc4342d8a4d95e18b957b898dbf5bfce28fca2780 (patch)
treefbaaaa50351a71f03b013b86ba32ef01bea19472 /drivers/infiniband
parentd1646f86a2a05a956adbb163c81a81bd621f055e (diff)
downloadop-kernel-dev-c4342d8a4d95e18b957b898dbf5bfce28fca2780.zip
op-kernel-dev-c4342d8a4d95e18b957b898dbf5bfce28fca2780.tar.gz
IB/mthca: Fix corner cases in max_rd_atomic value handling in modify QP
sae and sre bits should only be set when setting sra_max. Further, in the old code, if the caller specifies max_rd_atomic = 0, the sre and sae bits are still set, with the result that the QP ends up with max_rd_atomic = 1 in effect. Signed-off-by: Jack Morgenstein <jackm@mellanox.co.il> Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r--drivers/infiniband/hw/mthca/mthca_qp.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c
index e826c9f..d786ef4 100644
--- a/drivers/infiniband/hw/mthca/mthca_qp.c
+++ b/drivers/infiniband/hw/mthca/mthca_qp.c
@@ -747,9 +747,7 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
(MTHCA_FLIGHT_LIMIT << 24) |
- MTHCA_QP_BIT_SRE |
- MTHCA_QP_BIT_SWE |
- MTHCA_QP_BIT_SAE);
+ MTHCA_QP_BIT_SWE);
if (qp->sq_policy == IB_SIGNAL_ALL_WR)
qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
if (attr_mask & IB_QP_RETRY_CNT) {
@@ -758,9 +756,13 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
}
if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
- if (attr->max_rd_atomic)
+ if (attr->max_rd_atomic) {
+ qp_context->params1 |=
+ cpu_to_be32(MTHCA_QP_BIT_SRE |
+ MTHCA_QP_BIT_SAE);
qp_context->params1 |=
cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
+ }
qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
}
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