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| author | Michael S. Tsirkin <mst@mellanox.co.il> | 2005-09-26 09:29:33 -0700 |
|---|---|---|
| committer | Roland Dreier <rolandd@cisco.com> | 2005-09-26 09:38:34 -0700 |
| commit | f7ed3a5971da98acdc506bdbdef25cfe51c334a2 (patch) | |
| tree | 1e2cff00ff81b1a20be326d5b58e672846663102 /drivers/infiniband/hw/mthca/mthca_eq.c | |
| parent | 018771f435388f22f388eb8658c652086fb3633e (diff) | |
| download | op-kernel-dev-f7ed3a5971da98acdc506bdbdef25cfe51c334a2.zip op-kernel-dev-f7ed3a5971da98acdc506bdbdef25cfe51c334a2.tar.gz | |
[IB] mthca: fix off by one in clr_int calculation
We should use the first word of the clear interrupt register if
the bit we're after is < 32, not < 31.
Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/mthca/mthca_eq.c')
| -rw-r--r-- | drivers/infiniband/hw/mthca/mthca_eq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_eq.c b/drivers/infiniband/hw/mthca/mthca_eq.c index 78152a8..c81fa8e 100644 --- a/drivers/infiniband/hw/mthca/mthca_eq.c +++ b/drivers/infiniband/hw/mthca/mthca_eq.c @@ -836,7 +836,7 @@ int __devinit mthca_init_eq_table(struct mthca_dev *dev) dev->eq_table.clr_mask = swab32(1 << (dev->eq_table.inta_pin & 31)); dev->eq_table.clr_int = dev->clr_base + - (dev->eq_table.inta_pin < 31 ? 4 : 0); + (dev->eq_table.inta_pin < 32 ? 4 : 0); } dev->eq_table.arm_mask = 0; |
