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authorSonic Zhang <sonic.zhang@analog.com>2013-05-28 18:41:09 +0800
committerWolfram Sang <wsa@the-dreams.de>2013-06-12 20:39:07 +0200
commit8419c8debdc600b71fb89f0ffad80a6f436d80fe (patch)
tree5d0f1cfc0b37e7d00fa480ad77461a5af22b9683 /drivers/i2c
parentc80f52847c50109ca248c22efbf71ff10553dca4 (diff)
downloadop-kernel-dev-8419c8debdc600b71fb89f0ffad80a6f436d80fe.zip
op-kernel-dev-8419c8debdc600b71fb89f0ffad80a6f436d80fe.tar.gz
i2c: bfin-twi: Read and write the FIFO in loop
TWI transfer interrupts may be lost when system is heavily handling other interrupts, while current transfer handler depends on each accurate interrupt and misses some data in this case. Because there are 2 2-byte FIFOs in blackfin TWI controller, the occurrence of the data loss can be reduced by reading till the RX FIFO is empty and writing till the TX FIFO is full. Reported-by: Bob Maris <mail@maris-ee.eu> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c47
1 files changed, 27 insertions, 20 deletions
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 05080c4..13ea1c2 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -39,33 +39,40 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
unsigned short mast_stat = read_MASTER_STAT(iface);
if (twi_int_status & XMTSERV) {
+ if (iface->writeNum <= 0) {
+ /* start receive immediately after complete sending in
+ * combine mode.
+ */
+ if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | MDIR);
+ else if (iface->manual_stop)
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | STOP);
+ else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
+ iface->cur_msg + 1 < iface->msg_num) {
+ if (iface->pmsg[iface->cur_msg + 1].flags &
+ I2C_M_RD)
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) |
+ MDIR);
+ else
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) &
+ ~MDIR);
+ }
+ }
/* Transmit next data */
- if (iface->writeNum > 0) {
+ while (iface->writeNum > 0 &&
+ (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) {
SSYNC();
write_XMT_DATA8(iface, *(iface->transPtr++));
iface->writeNum--;
}
- /* start receive immediately after complete sending in
- * combine mode.
- */
- else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | MDIR);
- else if (iface->manual_stop)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | STOP);
- else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
- iface->cur_msg + 1 < iface->msg_num) {
- if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | MDIR);
- else
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) & ~MDIR);
- }
}
if (twi_int_status & RCVSERV) {
- if (iface->readNum > 0) {
+ while (iface->readNum > 0 &&
+ (read_FIFO_STAT(iface) & RCVSTAT)) {
/* Receive next data */
*(iface->transPtr) = read_RCV_DATA8(iface);
if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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