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author | Mathieu Poirier <mathieu.poirier@linaro.org> | 2017-08-02 10:21:57 -0600 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-08-28 16:05:47 +0200 |
commit | 0c3fc4d5fa26092853278145aca9b21fa52a3e93 (patch) | |
tree | 22445053dce96dc4922d04deb5f029a3aaec8c56 /drivers/hwtracing/coresight/coresight-etb10.c | |
parent | 4f871a9f0f6fbb8ab023cca1f0099bf152a5d618 (diff) | |
download | op-kernel-dev-0c3fc4d5fa26092853278145aca9b21fa52a3e93.zip op-kernel-dev-0c3fc4d5fa26092853278145aca9b21fa52a3e93.tar.gz |
coresight: Add barrier packet for synchronisation
When a buffer overflow happens the synchronisation patckets usually
present at the beginning of the buffer are lost, a situation that
prevents the decoder from knowing the context of the traces being
decoded.
This patch adds a barrier packet to be used by sink IPs when a buffer
overflow condition is detected. These barrier packets are then used
by the decoding library as markers to force re-synchronisation.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-etb10.c')
-rw-r--r-- | drivers/hwtracing/coresight/coresight-etb10.c | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 50f4846..4236030 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -200,8 +200,10 @@ static void etb_disable_hw(struct etb_drvdata *drvdata) static void etb_dump_hw(struct etb_drvdata *drvdata) { + bool lost = false; int i; u8 *buf_ptr; + const u32 *barrier; u32 read_data, depth; u32 read_ptr, write_ptr; u32 frame_off, frame_endoff; @@ -223,16 +225,24 @@ static void etb_dump_hw(struct etb_drvdata *drvdata) } if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) - & ETB_STATUS_RAM_FULL) == 0) + & ETB_STATUS_RAM_FULL) == 0) { writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); - else + } else { writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); + lost = true; + } depth = drvdata->buffer_depth; buf_ptr = drvdata->buf; + barrier = barrier_pkt; for (i = 0; i < depth; i++) { read_data = readl_relaxed(drvdata->base + ETB_RAM_READ_DATA_REG); + if (lost && *barrier) { + read_data = *barrier; + barrier++; + } + *(u32 *)buf_ptr = read_data; buf_ptr += 4; } @@ -354,6 +364,7 @@ static void etb_update_buffer(struct coresight_device *csdev, bool lost = false; int i, cur; u8 *buf_ptr; + const u32 *barrier; u32 read_ptr, write_ptr, capacity; u32 status, read_data, to_read; unsigned long offset; @@ -438,10 +449,17 @@ static void etb_update_buffer(struct coresight_device *csdev, cur = buf->cur; offset = buf->offset; + barrier = barrier_pkt; + for (i = 0; i < to_read; i += 4) { buf_ptr = buf->data_pages[cur] + offset; read_data = readl_relaxed(drvdata->base + ETB_RAM_READ_DATA_REG); + if (lost && *barrier) { + read_data = *barrier; + barrier++; + } + *(u32 *)buf_ptr = read_data; buf_ptr += 4; |