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| author | Imre Deak <imre.deak@intel.com> | 2016-02-12 18:55:12 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2016-02-22 17:44:36 +0200 |
| commit | 013ef6cfc411bfe4a6009eaa7dabb6531bbb41bb (patch) | |
| tree | 52d6a3484d04c04493767bc319334235feb2d6d7 /drivers/gpu | |
| parent | 9fb84d5a9299ac678dedc56487f394e5f68b91cb (diff) | |
| download | op-kernel-dev-013ef6cfc411bfe4a6009eaa7dabb6531bbb41bb.zip op-kernel-dev-013ef6cfc411bfe4a6009eaa7dabb6531bbb41bb.tar.gz | |
drm/i915/ibx: Ensure the HW is powered during PLL HW readout
The assumption when adding the intel_display_power_is_enabled() checks
was that if it returns success the power can't be turned off afterwards
during the HW access, which is guaranteed by modeset locks. This isn't
always true, so make sure we hold a dedicated reference for the time of
the access.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-4-git-send-email-imre.deak@intel.com
(cherry picked from commit 12fda3876d08519bdf6f0acc70dd35754b422ed5)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 892c53e..46a84bb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13659,7 +13659,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, { uint32_t val; - if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) + if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) return false; val = I915_READ(PCH_DPLL(pll->id)); @@ -13667,6 +13667,8 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); + intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); + return val & DPLL_VCO_ENABLE; } |
