diff options
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-07-28 11:52:45 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-07-28 16:28:31 -0700 |
| commit | 2704cf5fbd248871a745d210733c6319959d2b0c (patch) | |
| tree | 063f36ca865e51c0ebf45f2bf42b0c9e67c9f03e /drivers/gpu | |
| parent | 3bcf603f6d5d18bd9d076dc280de71f48add4101 (diff) | |
| download | op-kernel-dev-2704cf5fbd248871a745d210733c6319959d2b0c.zip op-kernel-dev-2704cf5fbd248871a745d210733c6319959d2b0c.tar.gz | |
drm/i915: flush plane control changes on ILK+ as well
After writing to the plane control reg we need to write to the surface
reg to trigger the double buffered register latch. On previous
chipsets, writing to DSPADDR was enough, but on ILK+ DSPSURF is the reg
that triggers the double buffer latch.
v2: write DSPADDR too to cover pre-965 chipsets
v3: use flush_display_plane instead, that's what it's for
v4: send the right patch
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 502efc3..a7a7b67 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1323,8 +1323,8 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, static void intel_flush_display_plane(struct drm_i915_private *dev_priv, enum plane plane) { - u32 reg = DSPADDR(plane); - I915_WRITE(reg, I915_READ(reg)); + I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); + I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); } /** |
