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authorMika Kuoppala <mika.kuoppala@linux.intel.com>2015-02-27 18:11:09 +0200
committerJani Nikula <jani.nikula@intel.com>2015-03-10 11:56:57 +0200
commit0cd0caad99a028568dd4a7c1b95777aadf4eb317 (patch)
tree852ad2a4bc3f9011401c3cc933e375754b04d6b7 /drivers/gpu
parent762e45836a047323defe9bdbbac534f0675ff027 (diff)
downloadop-kernel-dev-0cd0caad99a028568dd4a7c1b95777aadf4eb317.zip
op-kernel-dev-0cd0caad99a028568dd4a7c1b95777aadf4eb317.tar.gz
drm/i915: Do both mt and gen6 style forcewake reset on ivb probe
commit 05a2fb157e44 ("drm/i915: Consolidate forcewake code") failed to take into account that we have used to reset both the gen6 style and the multithreaded style forcewake registers. This is due to fact that ivb can use either, depending on how the bios has set up the machine. Mimic the old semantics before we have determined the correct variety and reset both before the ecobus probe. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Huang Ying <ying.huang@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c47a3ba..4e8fb89 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1048,8 +1048,14 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
/* We need to init first for ECOBUS access and then
* determine later if we want to reinit, in case of MT access is
- * not working
+ * not working. In this stage we don't know which flavour this
+ * ivb is, so it is better to reset also the gen6 fw registers
+ * before the ecobus check.
*/
+
+ __raw_i915_write32(dev_priv, FORCEWAKE, 0);
+ __raw_posting_read(dev_priv, ECOBUS);
+
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_MT_ACK);
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