diff options
author | Maarten Lankhorst <maarten.lankhorst@canonical.com> | 2013-07-07 10:37:48 +0200 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2013-07-08 10:52:07 +1000 |
commit | d2989b534ef6834ebf2425aecc040b894b567c91 (patch) | |
tree | f4db09ba08185f5f30a09566b4bc1cb88c984dc6 /drivers/gpu | |
parent | 1bb3f6a252c92cbc07884091e185a51b4ccb4f1d (diff) | |
download | op-kernel-dev-d2989b534ef6834ebf2425aecc040b894b567c91.zip op-kernel-dev-d2989b534ef6834ebf2425aecc040b894b567c91.tar.gz |
drm/nvc0/gr: fix gpc firmware regression
"drm/nve0-/gr: some new gpc registers can have multiple copies"
5ee86c4190f9e caused a regression for nvc0, because the bit indicating last
transfer has occured was no longer set, resulting in random system lockups.
Reported-by: Ronald Uitermark <ronald645@gmail.com>
Tested-by: Ronald Uitermark <ronald645@gmail.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h | 40 |
2 files changed, 23 insertions, 20 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc index b52f4a8..5547c1b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc @@ -352,6 +352,9 @@ ctx_xfer: // per-TPC mmio context xbit $r10 $flags $p1 // direction +#if !NV_PGRAPH_GPCX_UNK__SIZE + or $r10 4 // last +#endif mov $r11 0x4000 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0 ld b32 $r12 D[$r0 + #gpc_id] diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index 2afe75ce..f2b0dea 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h @@ -400,26 +400,26 @@ uint32_t nvc0_grgpc_code[] = { 0x0d98000c, 0x00e7f001, 0x016621f5, - 0xf101acf0, - 0xf04000b7, - 0x0c9850b3, - 0x0fc4b604, - 0x9800bcbb, - 0x0d98010c, - 0x060f9802, - 0x0800e7f1, - 0x016621f5, - 0x021521f5, - 0xf40601f4, -/* 0x0532: ctx_xfer_post */ - 0x17f11412, - 0x13f04afc, - 0x0d27f002, - 0xf50012d0, -/* 0x0543: ctx_xfer_done */ - 0xf5021521, - 0xf8047921, - 0x00000000, + 0xf001acf0, + 0xb7f104a5, + 0xb3f04000, + 0x040c9850, + 0xbb0fc4b6, + 0x0c9800bc, + 0x020d9801, + 0xf1060f98, + 0xf50800e7, + 0xf5016621, + 0xf4021521, + 0x12f40601, +/* 0x0535: ctx_xfer_post */ + 0xfc17f114, + 0x0213f04a, + 0xd00d27f0, + 0x21f50012, +/* 0x0546: ctx_xfer_done */ + 0x21f50215, + 0x00f80479, 0x00000000, 0x00000000, 0x00000000, |