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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-27 11:08:57 +0800 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-07 11:16:43 +0100 |
| commit | f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 (patch) | |
| tree | 9211554f0542ce636aa1f14ffe58cfa832efa04d /drivers/gpu | |
| parent | 93f5f7f1249e76a5e8afbdab53f90b10c41fdb61 (diff) | |
| download | op-kernel-dev-f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337.zip op-kernel-dev-f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337.tar.gz | |
agp/intel: Fix cache control for Sandybridge
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.
And set cache control to always LLC only by default on Gen6.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 748c263..16fca1d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -34,6 +34,7 @@ #include <linux/slab.h> #include <linux/swap.h> #include <linux/pci.h> +#include <linux/intel-gtt.h> static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
