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| author | Keith Packard <keithp@keithp.com> | 2009-06-11 22:28:56 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2009-06-18 15:54:11 -0700 |
| commit | b11248df4c0decb1e473d5025f237be32c0f67bb (patch) | |
| tree | 6251c3354774fa24945bc99aaa24d7e7f4b760b5 /drivers/gpu | |
| parent | e4b366996bc58a02b9dc35db3ef83f0454553f50 (diff) | |
| download | op-kernel-dev-b11248df4c0decb1e473d5025f237be32c0f67bb.zip op-kernel-dev-b11248df4c0decb1e473d5025f237be32c0f67bb.tar.gz | |
drm/i915: Add CLKCFG register definition
The CLKCFG register holds information about the GMCH plls and input clock
values.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f6237a0..544d567 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -569,6 +569,19 @@ #define C0DRB3 0x10206 #define C1DRB3 0x10606 +/* Clocking configuration register */ +#define CLKCFG 0x10c00 +#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */ +#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ +#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ +#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ +#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ +#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ +/* this is a guess, could be 5 as well */ +#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ +#define CLKCFG_FSB_1600_ALT (5 << 0) /* hrawclk 400 */ +#define CLKCFG_FSB_MASK (7 << 0) + /** GM965 GM45 render standby register */ #define MCHBAR_RENDER_STANDBY 0x111B8 |
