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| author | Oscar Mateo <oscar.mateo@intel.com> | 2018-05-08 14:29:34 -0700 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2018-05-11 15:57:53 +0300 |
| commit | 5ba700c73a89b0bace1a89a08e7a7eca5f011152 (patch) | |
| tree | 5dab27d79aecbed9a91ba147ffbeecc9b0922e54 /drivers/gpu | |
| parent | 5215eef35fcbbc8f9bd68adff90eb813e8c3b7cf (diff) | |
| download | op-kernel-dev-5ba700c73a89b0bace1a89a08e7a7eca5f011152.zip op-kernel-dev-5ba700c73a89b0bace1a89a08e7a7eca5f011152.tar.gz | |
drm/i915/icl: Wa_1406838659
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Rebased
- C, not lisp (Chris)
- Remove unintentional whitespaces (Mika)
- Fixed in C0 (Mika)
References: HSDES#1406838659
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-13-git-send-email-oscar.mateo@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_workarounds.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7cb2ddc..ce48427 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3848,6 +3848,9 @@ enum { #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) #define VFUNIT_CLKGATE_DIS (1 << 20) +#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) +#define CGPSF_CLKGATE_DIS (1 << 3) + /* * Display engine regs */ diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 2a4e3ee..942d322 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -755,6 +755,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER, I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) | GEN11_I2M_WRITE_DISABLE); + + /* Wa_1406838659:icl (pre-prod) */ + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0)) + I915_WRITE(INF_UNIT_LEVEL_CLKGATE, + I915_READ(INF_UNIT_LEVEL_CLKGATE) | + CGPSF_CLKGATE_DIS); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) |
