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authorChris Wilson <chris@chris-wilson.co.uk>2013-08-08 14:41:06 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-08-10 11:24:18 +0200
commitd46f1c3f1372e3a72fab97c60480aa4a1084387f (patch)
tree108839c739064c74491f993148a9049b59309676 /drivers/gpu/drm
parent2c22569bba8af6c2976d5f9479fe54a53a39966b (diff)
downloadop-kernel-dev-d46f1c3f1372e3a72fab97c60480aa4a1084387f.zip
op-kernel-dev-d46f1c3f1372e3a72fab97c60480aa4a1084387f.tar.gz
drm/i915: Allow the GPU to cache stolen memory
As a corollary to reviewing the interaction between LLC and our cache domains, the GPU PTE bits are independent of the CPU PAT bits. As such we can set the cache level on stolen memory based on how we wish the GPU to cache accesses to it. So we are free to set the same default cache levels as for normal bo, i.e. enable LLC cacheing by default where appropriate. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_stolen.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index e68c4b5..e20d649 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -287,9 +287,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev,
i915_gem_object_pin_pages(obj);
obj->stolen = stolen;
- obj->base.write_domain = I915_GEM_DOMAIN_GTT;
- obj->base.read_domains = I915_GEM_DOMAIN_GTT;
- obj->cache_level = I915_CACHE_NONE;
+ obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
+ obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
return obj;
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