diff options
| author | Rex Zhu <Rex.Zhu@amd.com> | 2018-03-22 14:38:37 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-23 09:42:42 -0500 |
| commit | 09695ad78f1f5f315c7e9c5090f0c7b846a43690 (patch) | |
| tree | 51912434d694d0fe1d1174719442aaec6d9ee468 /drivers/gpu/drm | |
| parent | 5b2933556fe02b3576758609918694a9e2a031d0 (diff) | |
| download | op-kernel-dev-09695ad78f1f5f315c7e9c5090f0c7b846a43690.zip op-kernel-dev-09695ad78f1f5f315c7e9c5090f0c7b846a43690.tar.gz | |
drm/amd/pp: clean header file hwmgr.h
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 15 |
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h index 6429dc2..d37d16e 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h @@ -27,6 +27,9 @@ struct pp_atomctrl_voltage_table; struct pp_hwmgr; struct phm_ppt_v1_voltage_lookup_table; +uint8_t convert_to_vid(uint16_t vddc); +uint16_t convert_to_vddc(uint8_t vid); + extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, uint32_t index, uint32_t value, uint32_t mask); diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index d742d9d..17f811d 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -39,9 +39,6 @@ struct pp_atomctrl_voltage_table; #define VOLTAGE_SCALE 4 -uint8_t convert_to_vid(uint16_t vddc); -uint16_t convert_to_vddc(uint8_t vid); - enum DISPLAY_GAP { DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ @@ -784,12 +781,12 @@ struct pp_hwmgr { uint32_t workload_setting[Workload_Policy_Max]; }; -extern int hwmgr_early_init(struct pp_hwmgr *hwmgr); -extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr); -extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); -extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr); -extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr); -extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr, +int hwmgr_early_init(struct pp_hwmgr *hwmgr); +int hwmgr_hw_init(struct pp_hwmgr *hwmgr); +int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); +int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr); +int hwmgr_hw_resume(struct pp_hwmgr *hwmgr); +int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id, enum amd_pm_state_type *user_state); |
