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authorStéphane Marchesin <marcheu@chromium.org>2014-05-22 20:32:46 -0700
committerThierry Reding <treding@nvidia.com>2014-06-09 12:02:31 +0200
commitccb8b12c4b72a5034a1e04efb68fe9a4682c1de0 (patch)
tree61c16862d2e9539a59ee7533cd5405ef98060423 /drivers/gpu/drm/tegra
parent1b0c7b48409c7faf241813bbf24588f3d676208f (diff)
downloadop-kernel-dev-ccb8b12c4b72a5034a1e04efb68fe9a4682c1de0.zip
op-kernel-dev-ccb8b12c4b72a5034a1e04efb68fe9a4682c1de0.tar.gz
drm/tegra: sor - Remove pixel clock rounding
The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/sor.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 93ae4fa..e22325f 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -876,9 +876,6 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output,
struct tegra_sor *sor = to_sor(output);
int err;
- /* round to next MHz */
- pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000;
-
err = clk_set_parent(clk, sor->clk_parent);
if (err < 0) {
dev_err(sor->dev, "failed to set parent clock: %d\n", err);
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