summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/tegra
diff options
context:
space:
mode:
authorThierry Reding <treding@nvidia.com>2014-06-05 16:29:46 +0200
committerThierry Reding <treding@nvidia.com>2014-06-09 12:02:50 +0200
commit0c90a184664abf657e3849f7e47e2e7fd1d93910 (patch)
tree73ec4f06876ade5e2ba101819204a432e81dc171 /drivers/gpu/drm/tegra
parent899451b787eb55d51c46468aaf99367c5f3420a1 (diff)
downloadop-kernel-dev-0c90a184664abf657e3849f7e47e2e7fd1d93910.zip
op-kernel-dev-0c90a184664abf657e3849f7e47e2e7fd1d93910.tar.gz
drm/tegra: sor - Enable only the necessary number of lanes
Instead of always enabling all four lanes, enable only the number probed from the link. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/sor.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index fefd26f0..7d2a5db 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -656,7 +656,7 @@ static int tegra_output_sor_enable(struct tegra_output *output)
value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
- value |= SOR_DP_LINKCTL_LANE_COUNT(4);
+ value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
/* start lane sequencer */
OpenPOWER on IntegriCloud