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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2018-06-25 14:02:58 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-06-27 21:44:01 +0200 |
| commit | aef13fd8426279fcd9e0b2b5b446d35c0d49ec5d (patch) | |
| tree | 9f719209bebfdfdb0f07edd48cb4cef12272af1f /drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | |
| parent | 09f380e3ba4103a32faf4fad35d90dc144578214 (diff) | |
| download | op-kernel-dev-aef13fd8426279fcd9e0b2b5b446d35c0d49ec5d.zip op-kernel-dev-aef13fd8426279fcd9e0b2b5b446d35c0d49ec5d.tar.gz | |
drm/sun4i: DW HDMI PHY: Add support for second PLL
Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select
between two clock parents.
Add code which reads second PLL from DT.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-19-jernej.skrabec@siol.net
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 3ba71af..46a3aa6 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -147,6 +147,7 @@ struct sun8i_hdmi_phy; struct sun8i_hdmi_phy_variant { bool has_phy_clk; + bool has_second_pll; void (*phy_init)(struct sun8i_hdmi_phy *phy); void (*phy_disable)(struct dw_hdmi *hdmi, struct sun8i_hdmi_phy *phy); @@ -160,6 +161,7 @@ struct sun8i_hdmi_phy { struct clk *clk_mod; struct clk *clk_phy; struct clk *clk_pll0; + struct clk *clk_pll1; unsigned int rcal; struct regmap *regs; struct reset_control *rst_phy; |
