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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2018-06-25 14:02:57 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-06-27 21:44:00 +0200 |
| commit | 09f380e3ba4103a32faf4fad35d90dc144578214 (patch) | |
| tree | 14aaa972dd53ac9aac11fa4ed3726e28d34a9727 /drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | |
| parent | 09773c532d30187f86a142901c27c93e629ce6ba (diff) | |
| download | op-kernel-dev-09f380e3ba4103a32faf4fad35d90dc144578214.zip op-kernel-dev-09f380e3ba4103a32faf4fad35d90dc144578214.tar.gz | |
drm/sun4i: Don't change clock bits in DW HDMI PHY driver
DW HDMI PHY driver and PHY clock driver share same registers. Make sure
that DW HDMI PHY setup code doesn't change any clock related bits.
During initialization, set PHY PLL parent bit to 0.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-18-jernej.skrabec@siol.net
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0..3ba71af 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -98,7 +98,7 @@ #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29) #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28) #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27) -#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL BIT(26) +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26) #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25) #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22) #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20) |
