diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2017-10-10 11:20:06 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-10-11 09:53:49 +0200 |
| commit | da184deeb8aeac6cadf45f01ce9bc4197940a059 (patch) | |
| tree | 99289bd002ec78525261e2ff90c7d6a80ec7f5ef /drivers/gpu/drm/sun4i/sun4i_hdmi.h | |
| parent | c4a9aec3dfe5203363c6c2f9fc62353f4898225e (diff) | |
| download | op-kernel-dev-da184deeb8aeac6cadf45f01ce9bc4197940a059.zip op-kernel-dev-da184deeb8aeac6cadf45f01ce9bc4197940a059.tar.gz | |
drm/sun4i: hdmi: Add support for A31's HDMI controller
The HDMI controller found in the A31 SoCs is slightly different
from the one already supported, which is found in the A10s:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock
This patch adds support for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-10-wens@csie.org
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun4i_hdmi.h')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_hdmi.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h index ee42ae7..9b97da3 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h @@ -59,10 +59,13 @@ #define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23) #define SUN4I_HDMI_PAD_CTRL1_REG 0x204 +#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN BIT(24) /* set on A31 */ #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23) #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22) #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20) #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19) +#define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18) +#define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17) #define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15) #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14) #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10) |
