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authorChen-Yu Tsai <wens@csie.org>2016-09-15 23:14:00 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-09-18 21:12:17 +0200
commite996e2089f25b84149ae82b5ddf37a263a7fcc71 (patch)
tree3e3e78fd7ab63cefdd9cd3cbb6b0e77867b99447 /drivers/gpu/drm/sun4i/sun4i_dotclock.c
parent9a8aa939ba33998f4c70c082dbd4d27a5ddcaaf6 (diff)
downloadop-kernel-dev-e996e2089f25b84149ae82b5ddf37a263a7fcc71.zip
op-kernel-dev-e996e2089f25b84149ae82b5ddf37a263a7fcc71.tar.gz
drm/sun4i: dotclock: Fix clock rate read back calcation
When reading back the divider set in the register, we mask off the bits that aren't part of the divider. Unfortunately the mask used here was not converted from the field width. Fix this by converting the field width to a proper bit mask. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun4i_dotclock.c')
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_dotclock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index 4332da4..1b6c225 100644
--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
@@ -62,7 +62,7 @@ static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
- val &= SUN4I_TCON0_DCLK_DIV_WIDTH;
+ val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1;
if (!val)
val = 1;
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