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| author | Koji Matsuoka <koji.matsuoka.xm@renesas.com> | 2016-05-16 11:28:15 +0900 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2016-11-15 01:44:50 +0200 |
| commit | fd1adef3bff0663c5ac31b45bc4a05fafd43d19b (patch) | |
| tree | 4e8895caca0db0d50f0551e4c134a6ba1cc99f90 /drivers/gpu/drm/rcar-du | |
| parent | 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 (diff) | |
| download | op-kernel-dev-fd1adef3bff0663c5ac31b45bc4a05fafd43d19b.zip op-kernel-dev-fd1adef3bff0663c5ac31b45bc4a05fafd43d19b.tar.gz | |
drm: rcar-du: Fix H/V sync signal polarity configuration
The VSL and HSL bits in the DSMR register set the corresponding
horizontal and vertical sync signal polarity to active high. The code
got it the wrong way around, fix it.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/rcar-du')
| -rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index aca26ee..a2ec6d8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -149,8 +149,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0); /* Signal polarities */ - value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL) - | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL) + value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0) + | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0) | DSMR_DIPM_DISP | DSMR_CSPM; rcar_du_crtc_write(rcrtc, DSMR, value); |
