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authorMichel Dänzer <michel.daenzer@amd.com>2014-08-01 17:22:09 +0900
committerAlex Deucher <alexander.deucher@amd.com>2014-08-05 08:53:47 -0400
commit404a6a512fdc6022d93fdd7085947f3a95f978c5 (patch)
treedef8f52e3040c8f6e6aab92b06a9051ea12add54 /drivers/gpu/drm/radeon
parent6b57f20cb5b708415fbab63847f8f8429b051af8 (diff)
downloadop-kernel-dev-404a6a512fdc6022d93fdd7085947f3a95f978c5.zip
op-kernel-dev-404a6a512fdc6022d93fdd7085947f3a95f978c5.tar.gz
drm/radeon: Only flush HDP cache from idle ioctl if BO is in VRAM
The HDP cache only applies to CPU access to VRAM. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index ab9abfa..99e4e0c 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -358,15 +358,17 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
struct drm_gem_object *gobj;
struct radeon_bo *robj;
int r;
+ uint32_t cur_placement = 0;
gobj = drm_gem_object_lookup(dev, filp, args->handle);
if (gobj == NULL) {
return -ENOENT;
}
robj = gem_to_radeon_bo(gobj);
- r = radeon_bo_wait(robj, NULL, false);
+ r = radeon_bo_wait(robj, &cur_placement, false);
/* Flush HDP cache via MMIO if necessary */
- if (rdev->asic->mmio_hdp_flush)
+ if (rdev->asic->mmio_hdp_flush &&
+ radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)
robj->rdev->asic->mmio_hdp_flush(rdev);
drm_gem_object_unreference_unlocked(gobj);
r = radeon_gem_handle_lockup(rdev, r);
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