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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-12-17 16:21:27 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-12-17 17:27:02 +0100
commitb45305fce5bb1abec263fcff9d81ebecd6306ede (patch)
tree5f8c074f2ceeb153bed7a0f28d631aec31b5eefc /drivers/gpu/drm/radeon
parent6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f (diff)
downloadop-kernel-dev-b45305fce5bb1abec263fcff9d81ebecd6306ede.zip
op-kernel-dev-b45305fce5bb1abec263fcff9d81ebecd6306ede.tar.gz
drm/i915: Implement workaround for broken CS tlb on i830/845
Now that Chris Wilson demonstrated that the key for stability on early gen 2 is to simple _never_ exchange the physical backing storage of batch buffers I've tried a stab at a kernel solution. Doesn't look too nefarious imho, now that I don't try to be too clever for my own good any more. v2: After discussing the various techniques, we've decided to always blit batches on the suspect devices, but allow userspace to opt out of the kernel workaround assume full responsibility for providing coherent batches. The principal reason is that avoiding the blit does improve performance in a few key microbenchmarks and also in cairo-trace replays. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: - Drop the hunk which uses HAS_BROKEN_CS_TLB to implement the ring wrap w/a. Suggested by Chris Wilson. - Also add the ACTHD check from Chris Wilson for the error state dumping, so that we still catch batches when userspace opts out of the w/a.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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