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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-11-01 19:01:36 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-01-08 18:42:22 -0500 |
| commit | de9ae7447aaa2fed8ae4aa9e6b7260915e5b4f7b (patch) | |
| tree | 3866f2fcf1aa0868dc4d9ec53b1bfd5dad50cf74 /drivers/gpu/drm/radeon/rv770d.h | |
| parent | 1a0041b8f99656a4600b587a491a1caa0e979e18 (diff) | |
| download | op-kernel-dev-de9ae7447aaa2fed8ae4aa9e6b7260915e5b4f7b.zip op-kernel-dev-de9ae7447aaa2fed8ae4aa9e6b7260915e5b4f7b.tar.gz | |
drm/radeon: implement pci config reset for r6xx/7xx (v3)
pci config reset is a low level reset that resets
the entire chip from the bus interface. It can
be more reliable if soft reset fails.
There's not much information still available on
r6xx, so r6xx is based on guess-work.
v2: put behind module parameter
v3: add IGP check
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/rv770d.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index 1ae2771..3cf1e29 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h @@ -100,14 +100,21 @@ #define CG_SPLL_FUNC_CNTL_2 0x604 #define SCLK_MUX_SEL(x) ((x) << 0) #define SCLK_MUX_SEL_MASK (0x1ff << 0) +#define SCLK_MUX_UPDATE (1 << 26) #define CG_SPLL_FUNC_CNTL_3 0x608 #define SPLL_FB_DIV(x) ((x) << 0) #define SPLL_FB_DIV_MASK (0x3ffffff << 0) #define SPLL_DITHEN (1 << 28) +#define CG_SPLL_STATUS 0x60c +#define SPLL_CHG_STATUS (1 << 1) #define SPLL_CNTL_MODE 0x610 #define SPLL_DIV_SYNC (1 << 5) +#define MPLL_CNTL_MODE 0x61c +# define MPLL_MCLK_SEL (1 << 11) +# define RV730_MPLL_MCLK_SEL (1 << 25) + #define MPLL_AD_FUNC_CNTL 0x624 #define CLKF(x) ((x) << 0) #define CLKF_MASK (0x7f << 0) |
