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authorAlex Deucher <alexander.deucher@amd.com>2013-08-20 20:29:05 -0400
committerChristian König <christian.koenig@amd.com>2014-02-18 16:11:32 +0100
commitb62d628bd63f61e9aea3b8fab2ec638680bf4aa4 (patch)
tree24d38dfe3996169ca839971241ac427b23ba5a39 /drivers/gpu/drm/radeon/radeon.h
parent82f79cc54b6a67c0b17aff4fb5ed43155ff3f0ea (diff)
downloadop-kernel-dev-b62d628bd63f61e9aea3b8fab2ec638680bf4aa4.zip
op-kernel-dev-b62d628bd63f61e9aea3b8fab2ec638680bf4aa4.tar.gz
drm/radeon/dpm: fill in some initial vce infrastructure
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 2b26feb..60c171c 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1259,6 +1259,15 @@ enum radeon_dpm_event_src {
RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
};
+enum radeon_vce_level {
+ RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
+ RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
+ RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
+ RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
+ RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
+ RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
+};
+
struct radeon_ps {
u32 caps; /* vbios flags */
u32 class; /* vbios flags */
@@ -1269,6 +1278,8 @@ struct radeon_ps {
/* VCE clocks */
u32 evclk;
u32 ecclk;
+ bool vce_active;
+ enum radeon_vce_level vce_level;
/* asic priv */
void *ps_priv;
};
@@ -1480,6 +1491,7 @@ struct radeon_dpm {
/* special states active */
bool thermal_active;
bool uvd_active;
+ bool vce_active;
/* thermal handling */
struct radeon_dpm_thermal thermal;
/* forced levels */
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