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authorAlex Deucher <alexander.deucher@amd.com>2014-01-16 18:02:59 -0500
committerAlex Deucher <alexander.deucher@amd.com>2014-01-20 18:20:56 -0500
commit10e9ffae463396c5a25fdfe8a48d7c98a87f6b85 (patch)
tree30433510563cf9b18705e63323ac6a93f2f1c3dc /drivers/gpu/drm/radeon/nid.h
parent8097d94116d0c17e774ba4c8256e774018dc2a46 (diff)
downloadop-kernel-dev-10e9ffae463396c5a25fdfe8a48d7c98a87f6b85.zip
op-kernel-dev-10e9ffae463396c5a25fdfe8a48d7c98a87f6b85.tar.gz
drm/radeon: fix surface sync in fence on cayman (v2)
We need to set the engine bit to select the ME and also set the full cache bit. Should help stability on TN and cayman. V2: fix up surface sync in ib execute as well Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/nid.h')
-rw-r--r--drivers/gpu/drm/radeon/nid.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 22421bc..d996033 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -1154,6 +1154,7 @@
# define PACKET3_DB_ACTION_ENA (1 << 26)
# define PACKET3_SH_ACTION_ENA (1 << 27)
# define PACKET3_SX_ACTION_ENA (1 << 28)
+# define PACKET3_ENGINE_ME (1 << 31)
#define PACKET3_ME_INITIALIZE 0x44
#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
#define PACKET3_COND_WRITE 0x45
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