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authorAlex Deucher <alexander.deucher@amd.com>2013-11-01 16:25:10 -0400
committerAlex Deucher <alexander.deucher@amd.com>2014-01-08 18:42:23 -0500
commitb5470b036e14d063655cc01d22ea5d727042860a (patch)
tree8420fd1eb90c039550fd922ea86a75f043b834bd /drivers/gpu/drm/radeon/ni.c
parentde9ae7447aaa2fed8ae4aa9e6b7260915e5b4f7b (diff)
downloadop-kernel-dev-b5470b036e14d063655cc01d22ea5d727042860a.zip
op-kernel-dev-b5470b036e14d063655cc01d22ea5d727042860a.tar.gz
drm/radeon: implement pci config reset for evergreen/cayman (v2)
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: put behind module parameter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 05a9009..9f11a55 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -174,6 +174,7 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
extern void evergreen_program_aspm(struct radeon_device *rdev);
extern void sumo_rlc_fini(struct radeon_device *rdev);
extern int sumo_rlc_init(struct radeon_device *rdev);
+extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
/* Firmware Names */
MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
@@ -1878,8 +1879,10 @@ int cayman_asic_reset(struct radeon_device *rdev)
reset_mask = cayman_gpu_check_soft_reset(rdev);
- if (!reset_mask)
- r600_set_bios_scratch_engine_hung(rdev, false);
+ if (reset_mask)
+ evergreen_gpu_pci_config_reset(rdev);
+
+ r600_set_bios_scratch_engine_hung(rdev, false);
return 0;
}
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