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authorYijing Wang <wangyijing@huawei.com>2013-09-09 21:13:08 +0800
committerBjorn Helgaas <bhelgaas@google.com>2013-10-04 14:31:09 -0600
commitc11592fea04901920236859898f5bc82b6c1a2f1 (patch)
treefaed7ae28a27bdf212d4ddf79c43155c49250fd1 /drivers/gpu/drm/radeon/evergreen.c
parent9db008d0d963f358c13381e86f5a042579216f06 (diff)
downloadop-kernel-dev-c11592fea04901920236859898f5bc82b6c1a2f1.zip
op-kernel-dev-c11592fea04901920236859898f5bc82b6c1a2f1.tar.gz
drm/radeon: use pcie_get_readrq() and pcie_set_readrq() to simplify code
Use pcie_get_readrq() and pcie_set_readrq() functions to simplify code. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c19
1 files changed, 6 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 555164e..871066a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1174,23 +1174,16 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
{
- u16 ctl, v;
- int err;
-
- err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
- if (err)
- return;
-
- v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
+ int readrq;
+ u16 v;
+ readrq = pcie_get_readrq(rdev->pdev);
+ v = ffs(readrq) - 8;
/* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
* to avoid hangs or perfomance issues
*/
- if ((v == 0) || (v == 6) || (v == 7)) {
- ctl &= ~PCI_EXP_DEVCTL_READRQ;
- ctl |= (2 << 12);
- pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
- }
+ if ((v == 0) || (v == 6) || (v == 7))
+ pcie_set_readrq(rdev->pdev, 512);
}
static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
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