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authorAlex Deucher <alexander.deucher@amd.com>2013-09-06 12:33:04 -0400
committerChristian König <christian.koenig@amd.com>2014-02-18 16:11:46 +0100
commita1d6f97c8cfa7c3554d0391c0b16505d1d97f380 (patch)
treeb99fc950e38a90fc25d9ccc066dd477c79699798 /drivers/gpu/drm/radeon/cik.c
parentb9fa18837610483b09a07f1419e6b9f333c46023 (diff)
downloadop-kernel-dev-a1d6f97c8cfa7c3554d0391c0b16505d1d97f380.zip
op-kernel-dev-a1d6f97c8cfa7c3554d0391c0b16505d1d97f380.tar.gz
drm/radeon/cik: enable/disable vce cg when encoding v2
Some of the vce clocks are automatic, others need to be manually enabled. For ease, just disable cg when vce is active. v2: rebased Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r--drivers/gpu/drm/radeon/cik.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index ecb16b1..2b31c32 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -75,6 +75,7 @@ extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
extern int cik_sdma_resume(struct radeon_device *rdev);
extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
extern void cik_sdma_fini(struct radeon_device *rdev);
+extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
static void cik_rlc_stop(struct radeon_device *rdev);
static void cik_pcie_gen3_enable(struct radeon_device *rdev);
static void cik_program_aspm(struct radeon_device *rdev);
@@ -6141,6 +6142,10 @@ void cik_update_cg(struct radeon_device *rdev,
cik_enable_hdp_mgcg(rdev, enable);
cik_enable_hdp_ls(rdev, enable);
}
+
+ if (block & RADEON_CG_BLOCK_VCE) {
+ vce_v2_0_enable_mgcg(rdev, enable);
+ }
}
static void cik_init_cg(struct radeon_device *rdev)
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