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| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-09-22 14:06:51 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-11-02 10:48:18 +0200 |
| commit | d5bcf0aa3f6fb396fc8099a4e5960f9274b0dae9 (patch) | |
| tree | 55aac9f37cd4dbd0d389470510232e828c5c20a2 /drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | |
| parent | a85f4a80784b34362568a0ff1f34aaa3357462a0 (diff) | |
| download | op-kernel-dev-d5bcf0aa3f6fb396fc8099a4e5960f9274b0dae9.zip op-kernel-dev-d5bcf0aa3f6fb396fc8099a4e5960f9274b0dae9.tar.gz | |
drm/omap: omap_display_timings: rename vsw to vsync_len
In preparation to move the stack to use the generic videmode struct for
display timing information rename the vsw member to vsync_len.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/dss/hdmi5_core.c')
| -rw-r--r-- | drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c index f986b32..3994474 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c @@ -299,7 +299,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, video_cfg->hblank = cfg->timings.hfront_porch + cfg->timings.hback_porch + cfg->timings.hsync_len; video_cfg->vblank_osc = 0; - video_cfg->vblank = cfg->timings.vsw + + video_cfg->vblank = cfg->timings.vsync_len + cfg->timings.vfp + cfg->timings.vbp; video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode; @@ -311,7 +311,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, video_cfg->v_fc_config.timings.vactive /= 2; video_cfg->vblank /= 2; video_cfg->v_fc_config.timings.vfp /= 2; - video_cfg->v_fc_config.timings.vsw /= 2; + video_cfg->v_fc_config.timings.vsync_len /= 2; video_cfg->v_fc_config.timings.vbp /= 2; } @@ -383,7 +383,7 @@ static void hdmi_core_video_config(struct hdmi_core_data *core, /* set vertical sync pulse width */ REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, - cfg->v_fc_config.timings.vsw, 5, 0); + cfg->v_fc_config.timings.vsync_len, 5, 0); /* select DVI mode */ REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, |
