diff options
author | Alexandre Courbot <acourbot@nvidia.com> | 2017-01-26 16:04:14 +0900 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2017-03-07 17:05:13 +1000 |
commit | c3433603cab756bcad0d8629c291f43b4f591b7d (patch) | |
tree | 5c44ad0417b9b36086107676b8dd39799b42e56c /drivers/gpu/drm/nouveau | |
parent | e9462417f1fedec381dd148cbc1d29d21bec4500 (diff) | |
download | op-kernel-dev-c3433603cab756bcad0d8629c291f43b4f591b7d.zip op-kernel-dev-c3433603cab756bcad0d8629c291f43b4f591b7d.tar.gz |
drm/nouveau/secboot: get start address of blob from ACR
The start address used for secure blobs is not unique to the ACR, but
rather blob-dependent. Remove the unique member stored in the ACR
structure and make the load function return the start address for the
current blob instead.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 7 |
3 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h index 580036d..9738340 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h @@ -49,7 +49,6 @@ struct nvkm_acr_func { * @boot_falcon: ID of the falcon that will perform secure boot * @managed_falcons: bitfield of falcons managed by this ACR * @optional_falcons: bitfield of falcons we can live without - * @start_address: virtual start address of the HS bootloader */ struct nvkm_acr { const struct nvkm_acr_func *func; @@ -58,7 +57,6 @@ struct nvkm_acr { enum nvkm_secboot_falcon boot_falcon; unsigned long managed_falcons; unsigned long optional_falcons; - u32 start_address; }; void *nvkm_acr_load_firmware(const struct nvkm_subdev *, const char *, size_t); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 814f9f2..8339514 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -754,9 +754,6 @@ acr_r352_prepare_hsbl_blob(struct acr_r352 *acr) hdr = acr->hsbl_blob; hsbl_desc = acr->hsbl_blob + hdr->header_offset; - /* virtual start address for boot vector */ - acr->base.start_address = hsbl_desc->start_tag << 8; - return 0; } @@ -813,8 +810,9 @@ acr_r352_load_blobs(struct acr_r352 *acr, struct nvkm_secboot *sb) } /** - * acr_r352_load() - prepare HS falcon to run the specified blob, mapped - * at GPU address offset. + * acr_r352_load() - prepare HS falcon to run the specified blob, mapped. + * + * Returns the start address to use, or a negative error value. */ static int acr_r352_load(struct nvkm_acr *_acr, struct nvkm_secboot *sb, @@ -861,7 +859,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_secboot *sb, nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off, bl_desc_size, 0); - return 0; + return hsbl_desc->start_tag << 8; } static int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index 813c4eb..b21e917 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -40,6 +40,7 @@ gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) struct nvkm_subdev *subdev = &gsb->base.subdev; struct nvkm_falcon *falcon = gsb->base.boot_falcon; struct nvkm_vma vma; + u32 start_address; int ret; ret = nvkm_falcon_get(falcon, subdev); @@ -61,9 +62,11 @@ gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) /* Load the HS bootloader into the falcon's IMEM/DMEM */ ret = sb->acr->func->load(sb->acr, &gsb->base, blob, vma.offset); - if (ret) + if (ret < 0) goto end; + start_address = ret; + /* Disable interrupts as we will poll for the HALT bit */ nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false); @@ -71,7 +74,7 @@ gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5); /* Start the HS bootloader */ - nvkm_falcon_set_start_addr(falcon, sb->acr->start_address); + nvkm_falcon_set_start_addr(falcon, start_address); nvkm_falcon_start(falcon); ret = nvkm_falcon_wait_for_halt(falcon, 100); if (ret) |