diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2016-03-11 13:09:28 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2016-03-14 10:13:46 +1000 |
| commit | a8b005fd527076b01b6df16c49f71416649ac859 (patch) | |
| tree | 1584c1921dd33ec84b35a9ec075aa6764d2eb001 /drivers/gpu/drm/nouveau | |
| parent | 608fd040b730a137ff771df43207aa702973d210 (diff) | |
| download | op-kernel-dev-a8b005fd527076b01b6df16c49f71416649ac859.zip op-kernel-dev-a8b005fd527076b01b6df16c49f71416649ac859.tar.gz | |
drm/nouveau/fifo/gk104: add sec plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/cla06f.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h index 663ecde..b5dec137 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h @@ -7,6 +7,7 @@ struct kepler_channel_gpfifo_a_v0 { __u16 chid; #define NVA06F_V0_ENGINE_SW 0x00000001 #define NVA06F_V0_ENGINE_GR 0x00000002 +#define NVA06F_V0_ENGINE_SEC 0x00000004 #define NVA06F_V0_ENGINE_MSVLD 0x00000010 #define NVA06F_V0_ENGINE_MSPDEC 0x00000020 #define NVA06F_V0_ENGINE_MSPPP 0x00000040 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 434335a..917ef0f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -63,6 +63,7 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) case NVKM_ENGINE_CE1 : case NVKM_ENGINE_CE2 : return 0x0000; case NVKM_ENGINE_GR : return 0x0210; + case NVKM_ENGINE_SEC : return 0x0220; case NVKM_ENGINE_MSPDEC: return 0x0250; case NVKM_ENGINE_MSPPP : return 0x0260; case NVKM_ENGINE_MSVLD : return 0x0270; @@ -340,6 +341,7 @@ gk104_fifo_gpfifo[] = { { NVA06F_V0_ENGINE_SW | NVA06F_V0_ENGINE_GR, BIT_ULL(NVKM_ENGINE_SW) | BIT_ULL(NVKM_ENGINE_GR) }, + { NVA06F_V0_ENGINE_SEC , BIT_ULL(NVKM_ENGINE_SEC ) }, { NVA06F_V0_ENGINE_MSVLD , BIT_ULL(NVKM_ENGINE_MSVLD ) }, { NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) }, { NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) }, |
