summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
diff options
context:
space:
mode:
authorBen Skeggs <bskeggs@redhat.com>2015-01-14 12:34:00 +1000
committerBen Skeggs <bskeggs@redhat.com>2015-01-22 12:17:47 +1000
commit8700287be2b12d091d477fe0568c3858bdedf4e7 (patch)
tree40a4b59a39a0f77f34b31d30db08b2fd51b9af37 /drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
parentfd8666f7db94afc1b63b8439d902783b27a2f27f (diff)
downloadop-kernel-dev-8700287be2b12d091d477fe0568c3858bdedf4e7.zip
op-kernel-dev-8700287be2b12d091d477fe0568c3858bdedf4e7.tar.gz
drm/nouveau/sw: rename from software (no binary change)
Shorter device name, make consistent with our engine enums. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 59b6baa..dfb610f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -37,7 +37,7 @@
#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
-#include <engine/software.h>
+#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
@@ -61,7 +61,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -80,7 +80,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
@@ -99,7 +99,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -119,7 +119,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -139,7 +139,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
+ device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
OpenPOWER on IntegriCloud