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authorBen Skeggs <bskeggs@redhat.com>2012-05-01 10:14:07 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-05-24 16:56:00 +1000
commit67b342efc761046a22b73c327837479b58613a41 (patch)
tree86a7d34699e48b855a8a99d8aaab3465cd2f8cd3 /drivers/gpu/drm/nouveau/nv50_graph.c
parent906c033e276877c1374c9159976b05746af3c86d (diff)
downloadop-kernel-dev-67b342efc761046a22b73c327837479b58613a41.zip
op-kernel-dev-67b342efc761046a22b73c327837479b58613a41.tar.gz
drm/nouveau/fifo: remove all the "special" engine hooks
All the places this stuff is actually needed tends to be chipset-specific anyway, so we're able to just inline the register bashing instead. The parts of the common code that still directly touch PFIFO temporarily have conditionals, these will be removed in subsequent commits that will refactor the fifo modules into engine modules like graph/mpeg etc. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_graph.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index a46e060..d262e31 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -262,7 +262,6 @@ nv50_graph_context_del(struct nouveau_channel *chan, int engine)
struct nouveau_gpuobj *grctx = chan->engctx[engine];
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
unsigned long flags;
@@ -272,7 +271,7 @@ nv50_graph_context_del(struct nouveau_channel *chan, int engine)
return;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
- pfifo->reassign(dev, false);
+ nv_wr32(dev, NV03_PFIFO_CACHES, 0);
nv50_graph_fifo_access(dev, false);
if (nv50_graph_channel(dev) == chan)
@@ -283,7 +282,7 @@ nv50_graph_context_del(struct nouveau_channel *chan, int engine)
dev_priv->engine.instmem.flush(dev);
nv50_graph_fifo_access(dev, true);
- pfifo->reassign(dev, true);
+ nv_wr32(dev, NV03_PFIFO_CACHES, 1);
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
nouveau_gpuobj_ref(NULL, &grctx);
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